Solid state memories (SSMs) often comprise one or more arrays of individually programmable memory cells configured to store data by the application of write currents to the cells to store a sequence of bits. The stored bits can be subsequently read during a read operation by applying suitable read currents and sensing voltage drops across the cells.
Some SSM cell configurations employ a resistive sense element coupled to a channel based switching device. The resistive element can be programmed to different resistances to represent different bit states. The switching device provides selective access to the resistive sense element during read and write operations. The cells in an SSM array are often arranged into rows and columns, and are individually accessed by asserting various control lines such as word lines, bit lines and source lines. Some SSM configurations utilize a common source plane in lieu of individual source lines.
A continued trend is to provide SSM arrays with larger data capacities and smaller manufacturing process feature sizes (e.g., F=45 nanometers, nm or F=32 nm, where F is a minimum feature dimension of the associated manufacturing process.). While operable in providing greater data storage capacity and density levels, the use of increasingly larger arrays and/or smaller feature sizes can lead to significant increases in process parameter variations, such as variations in the electrical resistance of the control lines.
Depending on the location of a given cell within an array, it has been found that the electrical resistance of a line from an associated driver to the cell may be substantially equal in magnitude to the programmed resistance of the cell. This can make it difficult to accurately sense the programmed state of the cell, particularly when relatively small magnitudes of sense voltages are used.